Architectures for the next generation of computing.
Design methods for emerging hardware: silicon photonics, reconfigurable architectures, and the systems they enable.
Design methods for emerging hardware.
LECS investigates the architectural foundations of post-CMOS computing — from silicon photonic interconnects and reconfigurable arrays to near-term quantum processors. Our work spans device-level modelling, system-level simulation, and FPGA prototyping, in close collaboration with industry and partner institutions across Montréal and Europe.
Nine intertwined research directions.
Each direction is led by a graduate researcher or postdoctoral fellow. Together they form a coherent agenda on emerging computing systems, from the physical layer to the toolchain.
Silicon photonic interconnects
Microring-resonator-based on-chip optical networks that move data with the bandwidth and energy efficiency electrical wires cannot.
Reconfigurable architectures
Coarse-grained reconfigurable arrays and FPGA-based accelerators that adapt to workload demands at runtime.
Network-on-Chip
Scalable interconnect fabrics — electrical, optical and hybrid — for many-core systems-on-chip.
Quantum computing
Compilation, mapping and control-stack design for near-term quantum hardware.
Edge AI accelerators
Custom datapaths for convolutional and recurrent inference at the edge, under tight area and power budgets.
Neuromorphic architectures
Spiking and analog substrates for event-driven sensing and learning.
Manycore SoCs
Architecture and design-space exploration of heterogeneous many-core processors.
Approximate computing
Quality-configurable arithmetic and memory for energy-proportional computation.
FPGA prototyping
Hardware-in-the-loop validation of novel architectures on contemporary FPGAs.
A small group, broad interests.
The group is led by Prof. Sébastien Le Beux and includes one postdoctoral fellow, four doctoral candidates, two master's students, and one visiting researcher, with active alumni in industry.
Sébastien Le Beux is Associate Professor in the Department of Electrical and Computer Engineering at Concordia University. From 2010 to 2019 he was associate professor at École Centrale de Lyon, where he led nanoprocessors research activities at the Lyon Institute of Nanotechnology (CNRS).
News from the group.
Recent papers, awards, defences, and collaborations. Click through for the full abstract, authors, and the publisher / arXiv link.
LECS paper accepted at DATE 2026
“Variability-aware mapping for silicon photonic NoCs” has been accepted at the Design, Automation and Test in Europe Conference. The work introduces a statistical mapping flow that accounts for fabrication drift across waveguide arrays.
Frédéric Gagné receives FRQNT master’s scholarship
Frédéric Gagné has been awarded a Fonds de recherche du Québec — Nature et technologies graduate scholarship to support his work on energy-proportional neuromorphic inference.
Invited keynote at NanoArch 2026
Prof. Le Beux delivered a keynote on emerging-technology architectures at the 21st IEEE/ACM International Symposium on Nanoscale Architectures.
Lightweight Yet Powerful: Optimized Tightly Coupled Hyperdimensional Computing Accelerators
Hyperdimensional Computing (HDC) is a hardware-friendly machine learning paradigm that encodes data into high-dimensional binary hypervectors, enabling efficient computation through lightweight bitwise operations.
Robust GHZ State Preparation via Majority-Voted Boundary Measurements
Preparing high-fidelity Greenberger-Horne-Zeilinger (GHZ) states on noisy quantum hardware remains challenging due to cumulative gate errors and decoherence.
NSERC Discovery Grant renewed for 2026–2031
The group’s NSERC Discovery Grant on silicon photonic interconnects has been renewed for a further five-year term.
Selected publications.
Filter by year, topic, author, or search across titles and venues. The supervisor's name is highlighted in each row.
Open positions — MSc & PhD.
We are actively recruiting motivated students at the MSc and PhD levels to work on hardware architectures using emerging technologies. Candidates with backgrounds in computer architecture, hardware programming (VHDL/Verilog), system-level simulation, optimization, or neural networks are particularly encouraged to apply.
Women and minorities are strongly encouraged to apply. Send a CV, transcripts, and a brief statement of motivation to slebeux (at) encs.concordia.ca.