A comprehensive compact model for the design of all-spin-logic based circuits

Abstract By relying on pure spin transmission, low-frequency charge-spin conversion, and neuron-like mechanism, All Spin Logic (ASL) has the potential to outperform CMOS technology in logic design and especially in neuromorphic computing, with improved fabrication process and material technology in the future. As ASL technology is gaining in maturity, compact models are needed to fill the gap between application requirements and circuit fabrication. However, defining such a model is a tedious task due to the numerous physical parameters to consider and the need for flexibility to explore design tradeoffs. In this paper, we propose an accurate, generic, scalable, and easy-to-use compact model for ASL devices. The model has been validated by comparing with experimental results, which allows investigating the impact of device characteristics such as channel length and channel width on the propagation delay. The model has been implemented in Cadence using in Verilog-A, which allows running transient simulations and comparing the implementations of 4-bit adder and multiplier circuits regarding the area, energy and delay metrics.