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Analysis of Energy-Delay-Product of a 3D Vertical Nanowire FET Technology

I. O’Connor, A. Poittevin, S. Le Beux, A. Bosio, Z. Stanojevic, O. Baumgartner, C. Mukherjee, C. Maneux, J. Trommer, T. Mikolajick, G. Larrieu

Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon · 2021 · DOI: 10.1109/EuroSOI-ULIS53016.2021.9560180

Neuromorphic architectures

Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon 2021 I. O’Connor, A. Poittevin, S. Le Beux, A. Bosio, Z. Stanojevic, O. Baumgartner, C. Mukherjee, C. Maneux, J. Trommer, T. Mikolajick, G. Larrieu

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Abstract

To sustain transistor scaling beyond lateral 7nm devices, gate-all-around (GAA) junction-less vertical nanowire field effect transistors (VNWFET) are a promising alternative. This work analyses the energy-delay-product (EDP) for a junction-less 3D vertical gate-all-around nanowire FET technology, with a physical channel length of 14nm. Comparisons with the EDP of a baseline 7nm FinFET technology are carried out. The analysis motivates a new 3D neural network compute cube (N2C2) concept. Our results show that a 10x gain in EDP can be achieved for a physical VNWFET gate length of 14nm.

Citation

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@inproceedings{i2021cedf6aba407f585d9183c20e22fa3aef9a7ad2c6,
  title  = {Analysis of Energy-Delay-Product of a 3D Vertical Nanowire FET Technology},
  author = {I. O’Connor and A. Poittevin and S. Le Beux and A. Bosio and Z. Stanojevic and O. Baumgartner and C. Mukherjee and C. Maneux and J. Trommer and T. Mikolajick and G. Larrieu},
  booktitle = {Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon},
  year   = {2021},
  doi    = {10.1109/EuroSOI-ULIS53016.2021.9560180}
}

Acknowledgements

This work was supported in part by the Natural Sciences and Engineering Research Council of Canada (NSERC) Discovery Grants programme and by the Fonds de recherche du Québec — Nature et technologies (FRQNT).