A ReRAM-Based Accelerator with Unified Sparse Graph Representation

Graph accelerators are emerging as an effective solution for analyzing large-scale graphs. These accelerators often leverage near-memory computing to minimize data movement and increase memory bandwidth. Due to the high sparsity of real-world graphs, state-of-the-art accelerators store graph data in compressed formats in main memory and process subgraphs using local memory crossbars. However, this approach introduces data conversion overhead and computational inefficiency caused by inconsistent graph representations across the memory hierarchy. This paper proposes a conversion-free graph accelerator based on a unified Coordinate List (COO) representation shared between main memory and graph engines. The proposed architecture consists of an array of graph engines interconnected through a 2D mesh Network-on-Chip, each operating directly on compressed graph data. This design maximizes local crossbar utilization and eliminates host-side format conversion overhead. The proposed design is evaluated against four state-of-the-art accelerators. It achieves average speedups of 10.4× over TARe, 7.8× over SparseMEM, and 7.5× over RPBFS, and outperforms GraphR by two orders of magnitude. The corresponding energy-delay product reductions range from 10.8× over SparseMEM to six orders of magnitude over GraphR and TARe.