Towards Maximum Energy Efficiency in Nanophotonic Interconnects with Thermal-Aware On-Chip Laser Tuning

Nanophotonic is an emerging technology considered as one of the key solutions for future generation on-chip interconnects. However, silicon photonic devices are highly sensitive to temperature variation. Under a given chip activity, this leads to a lower laser efficiency and a drift of wavelengths of optical devices (on-chip lasers and microring resonators (MRs)), which results in a higher Bit Error Ratio (BER). In this paper, we propose to jointly tune the on-chip lasers and and MRs in order to align the wavelengths of the emitted signals with the resonant wavelengths of the MRs. Our method allows significant improvements of the power consumption with regard to the related methods, while meeting the BER requirement. Compared to methods for which laser tuning is not possible, results show that a combined tuning of laser and MRs leads to 53 percent energy reduction when the uniform chip activity decreases from 20 to 5 percent. BER-energy tradeoffs have been explored and allow strategies to be defined to minimize either the energy, or the BER. As a key result, we have shown that, under specific chip activities, increasing the laser power consumption allows both energy and BER to be improved. This trend has been observed for a MWSR channel interconnecting 12 interfaces.