Lightweight Yet Powerful: Optimized Tightly Coupled Hyperdimensional Computing Accelerators

Hyperdimensional Computing (HDC) is a hardware-friendly machine learning paradigm that encodes data into high-dimensional binary hypervectors, enabling efficient computation through lightweight bitwise operations. Existing HDC accelerators, often implemented on FPGAs, typically rely on custom instruction sets and co-processor designs to optimize performance. However, these architectures face programmability challenges and incur significant control overhead when interacting with the main processor. To overcome these limitations, we present a methodology for designing and optimizing tightly coupled HDC accelerators. The proposed method produces accelerators enhanced with a controller capable of decoding instructions corresponding to key HDC kernels, thereby reducing communication overhead and improving throughput. To validate the approach, we implemented the accelerator at the RTL level and modeled the entire system in SystemVerilog. Experimental results demonstrate that, compared to state-of-the-art architectures, the proposed method reduces software code size by up to 98% while achieving a $(3 \times$) speedup.