Full-adder circuit design based on all-spin logic device

Limiting or reducing the power consumption of the digital circuits for calculation is now the main concern in nanoelectronic domain. For this purpose, spintronic devices are proposed to combine or even replace complementary metal-oxide semiconductor (CMOS) technology for the implementation of integrated circuits. One of the most promising solutions is all spin logic (ASL) device, due to a low power consumption, high switching speed and the compatibility with CMOS. In this paper, we propose a one-bit full-adder and a multi-bits adder circuits relying on ASL devices. The performances of the circuits are evaluated with transient simulation using a compact model of ASL devices developed in Cadence. Finally, ASL device parameters are explored for optimization.